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PRELIMINARY
AM79C981
Integrated Multiport Repeater PlusTM (IMR+TM)
DISTINCTIVE CHARACTERISTICS
s Enhanced version of AMD's Am79C980 Integrated Multiport RepeaterTM (IMRTM) chip with the following enhancements: -- Additional management port features -- Minimum mode provides support for an extra four LED outputs per port for additional status in non-intelligent repeater designs -- Pin/socket-compatible with the Am79C980 IMR chip -- Fully backward-compatible with existing IMR device designs s Interfaces directly with the Am79C987 HIMIBTM device to build a fully managed multiport repeater s CMOS device features high integration and low power with a single +5 V supply s Repeater functions comply with IEEE 802.3 Repeater Unit specifications s Eight integral 10BASE-T transceivers utilize the required predistortion transmission technique s Attachment unit interface (AUI) port allows connectivity with 10BASE-5 (Ethernet) and 10BASE-2 (Cheapernet) networks, as well as 10BASE-F and/or Fiber Optic Inter-Repeater Link (FOIRL) segments s On-board PLL, Manchester encoder/decoder, and FIFO s Expandable to increase number of repeater ports s All ports can be separately isolated (partitioned) in response to excessive collision conditions or fault conditions s Network management and optional features are accessible through a dedicated serial management port s Twisted-pair Link Test capability conforming to the 10BASE-T standard. The receive Link Test function can be optionally disabled through the management port to facilitate interoperability with devices that do not implement the Link Test function s Programmable option of Automatic Polarity Detection and Correction permits automatic recovery due to wiring errors s Full amplitude and timing regeneration for retransmitted waveforms s Preamble loss effects eliminated by deep FIFO
GENERAL DESCRIPTION
The Integrated Multiport Repeater Plus (IMR+) chip is a VLSI circuit that provides a system-level solution to designing a compliant 802.3 repeater incorporating 10BASE-T transceivers. The device integrates the Repeater functions specified by Section 9 of the IEEE 802.3 standard and Twisted-Pair Transceiver functions complying with the 10BASE-T standard. The AM79C981 provides eight integral twisted-pair medium attachment units (MAUs) and an attachment unit interface (AUI) port in an 84-pin plastic leaded chip carrier (PLCC). A network based on the 10BASE-T standard uses unshielded twisted-pair cables, thereby providing an economical solution to networking by allowing the use of low-cost unshielded twisted-pair (UTP) cable or existing telephone wiring. The total number of ports per repeater unit can be increased by connecting multiple IMR+ devices through
Publication# 17306 Rev: B Amendment/0 Issue Date: January 1999
their expansion ports, minimizing the total cost per repeater port. Furthermore, a general-purpose attachment unit interface (AUI) provides connection capability to 10BASE-5 (Ethernet) and 10BASE-2 (Cheapernet) coaxial networks, as well as 10BASE-F and/or Fiber Optic Inter-Repeater Link (FOIRL) fiber segments. Network management and test functions are provided through TTL-compatible I/O pins. The IMR+ device interfaces directly with AMD's Am79C987 Hardware Implemented Management Information BaseTM (HIMIB) chip to build a fully managed multiport repeater as specified by the IEEE 802.3 (Layer Management for 10 Mb/s Baseband Repeaters) standard. When the IMR+ and HIMIB devices are interconnected, complete repeater and per-port statistics are maintained and can be accessed on demand using a simple 8-bit parallel interface. 1-71
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
AMD
PRELIMINARY The device is fabricated in CMOS technology and requires a single +5 V supply.
For application examples on building a fully managed repeater using the IMR+ and HIMIB devices, refer to AMD's IEEE 802.3 Repeater Technical Manual (PID#17314A) and the ISA-HUBTM User Manual (PID # 17642A).
BLOCK DIAGRAM
DI CI DO Phase = Locked Loop AUI Port RX MUX Manchester Decoder FIFO Preamble Jam Sequence FIFO Control TX MUX
RXD TXD TXP
TP Port 0
Manchester Encoder
RXD TXD TXP TP Port 7 IMR+ Chip Control Expansion Port Partitioning Link Test RST Reset
REQ ACK COL DAT JAM
X1 X2
SI Clock Gen Timers Test and Management Port SO SCLK TEST CRS STR 17306B-1
RELATED AMD PRODUCTS
Part No. Am79C98 Am79C100 Am7996 Am79C987 Am79C940 Am7990 Am79C90 Am79C900 Am79C960 Am79C961 Am79C965 Am79C970 Am79C974 Description Twisted Pair Ethernet Transceiver (TPEX) Twisted Pair Ethernet Transceiver Plus (TPEX+) IEEE 802.3/Ethernet/Cheapernet Transceiver Hardware Implemented Management Information BaseTM (HIMIBTM) Media Access Controller for Ethernet (MACETM) Local Area Network Controller for Ethernet (LANCE) CMOS Local Area Network Controller for Ethernet (C-LANCE) Integrated Local Area Communications ControllerTM (ILACCTM) PCnet-ISA Single-Chip Ethernet Controller (for ISA bus) PCnet-ISA+ Single-Chip Ethernet Controller for ISA (with Microsoft(R) Plug n' Play(R) Support) PCnet-32 Single-Chip 32-Bit Ethernet Controller PCnet-PCI Single-Chip Ethernet Controller (for PCI bus) PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems
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CONNECTION DIAGRAM
PLCC
CI+ CI- DI+ DI- RXD0+ RXD0- AVSS RXD1+ RXD1- RXD2+ RXD2- RDX3+ RXD3- AVDD
RXD4+ RXD4- RXD5+ RXD5- RXD6+ RXD6-
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 DO- DO+ TXD0+ TXD0- DVSS TXP1+ TXP1- DVDD TXD1+ TXD1- TXP1+ TXP1- TXD2+ TXD2- TXP2+ TXP2- DVDD TXD3+ TXD3- DVSS TXP3+ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 TXP3- SO DVSS STR DVSS CRS SI SCLK TEST RST DVDD X1 X2 DVSS ACK COL DVDD JAM DVSS DAT REQ RXD7- TXD7+ TXD7- DVSS TXP7+ TXP7- DVDD TXD6+ TXD6- TXP6+ TXP6- TXD5+ TXD5- TXP5+ TXP5- DVDD TXD4+ TXD4- DVSS TXP4+ TXP4-
IMR+ Chip AM79C981
RXD7+
17306B-2
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LOGIC SYMBOL
DVDD DO+ DO- AUI DI+ DI- CI+ CI- Management Port SCLK SI SO X2 X1 TEST RST DVSS
AVDD TXD+ TXP+ TXD- TXP- RXD+ RXD- Twisted Pair Ports (8 Ports)
AM79C981
DAT JAM ACK COL REQ CRS STR Expansion Port
AVSS
Port Activity Monitor
17306B-3
LOGIC DIAGRAM
AUI
Management Port
Repeater State Machine
Expansion Port
Twisted Pair Port 0
Twisted Pair Port 7
17306B-4
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ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below.
AM79C981
J
C
OPTIONAL PROCESSING Blank = Standard Processing
OPERATING CONDITIONS C = Commercial (0C to +70C)
PACKAGE TYPE J = 84-Pin Plastic Leaded Chip Carrier (PL 084)
SPEED Not Applicable DEVICE NUMBER/DESCRIPTION AM79C981 Integrated Multiport Repeater Plus (IMR+)
Valid Combinations AM79C981 JC
Valid Combinations Valid combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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PIN DESCRIPTION ACK
Acknowledge Input, Active LOW When this input is asserted, it signals to the requesting IMR+ device that it may control the DAT and JAM pins. If the IMR+ chip is not requesting control of the DAT line (REQ pin HIGH), then the assertion of the ACK signal indicates the presence of valid collision status on the JAM or valid data on the DAT line.
When ACK is not asserted, DAT is in high impedance. If REQ and ACK are both asserted, then DAT is an output. If ACK is asserted and REQ not asserted, then DAT is an input. This pin needs to be either pulled up or pulled down through a high-value resistor.
DI+, DI-
Data In Input AUI port differential receiver. Signals comply with IEEE 802.3, Section 7.
AVDD
Analog Power Power Pin These pins supply the +5 V to the RXD+/- receivers, the DI+/- and CI+/- receivers, the DO+/- drivers, the internal PLL, and the internal voltage reference of the IMR+ device. These power pins should be decoupled and kept separate from other power and ground planes.
DO+, DO-
Data Out Output AUI port differential driver. Signals comply with IEEE 802.3, Section 7.
DVDD
Digital Power Power Pin These pins supply +5 V to the logic portions of the IMR+ chip and the TXP+/-, TXD+/-, and DO+/- line drivers.
AVSS
Analog Ground Ground Pin These pins are the 0 V reference for AVDD.
COL
Expansion Collision Input, Active LOW When this input is asserted by an external arbiter, it signifies that more than one IMR+ device is active and that each IMR+ device should generate the Collision Jam sequence independently.
DVSS
Digital Ground Ground Pin These pins are the 0 V reference for DVDD.
DVDD Pin # 19 28 43, 49 59 68 DVSS Pin # 16 31 35, 37, 46, 51 56 71 Function TP ports 0 & 1 drivers TP ports 2 & 3 drivers Core logic and expansion and control pins TP ports 4 & 5 drivers TP ports 6 & 7 drivers
CI+, CI-
Control In Input AUI port differential receiver. Signals comply with IEEE 802.3, Section 7.
CRS
Carrier Sense Output The states of the internal carrier sense signals for the AUI port and the eight twisted-pair ports are serially output on this pin continuously. The output serial bit stream is synchronized to the X1 clock.
JAM
Jam Input/Output/3-State When JAM is asserted, the state of DAT will indicate either a multiport (DAT = 0) or single-port (DAT = 1) collision condition. When ACK is not asserted, JAM is in high impedance. If REQ and ACK are both asserted, then JAM is an output. If ACK is asserted and REQ not asserted, then JAM is an input. This pin needs to be either pulled up or pulled down through a high-value resistor.
DAT
Data Input/Output/3-State In non-collision conditions, the active IMR+ device will drive DAT with NRZ data, including regenerated preamble. During collision, when JAM = HIGH, DAT is used to signal a multiport (DAT = 0) or single-port (DAT = 1) condition. 1-76
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REQ
Request Output, Active LOW This pin is driven LOW when the IMR+ chip is active. An IMR+ chip is active when it has one or more ports receiving or colliding or is in the state where it is still transmitting data from the internal FIFO. The assertion of this signal signifies that the IMR+ device is requesting the use of the DAT and JAM lines for the transfer of repeated data or collision status to other IMR+ devices.
input. In Minimum mode, the SO pin is used to serially output the various status information based on the state of the SI and SCLK pins.
SCLK 0 0 1 1 SI 0 1 0 1 SO Output TP Ports Receive Polarity Status + AUI SQE Test Error Status Bit Rate Error (all ports) TP Ports Link Status + AUI Loopback Status Port Partitioning Status (all ports)
RST
Reset Input, Active LOW Driving this pin LOW resets the internal logic of the IMR+ device. Reset should be synchronized to the X1 clock if either expansion or port activity monitor is used.
STR
Store Input/Output As an output, this pin goes HIGH for two X1 clock cycle times after the nine carrier sense bits are output on the CRS pin. Note that the carrier sense signals arriving from each port are latched internally, so that an active transition is remembered between samples. The accuracy of the carrier sense signals produced in this manner is 10 bit times (1 s). When used in conjunction with the HIMIB device, the STR pin will be configured as an input automatically after a hardware reset. The HIMIB device uses this input to communicate with the IMR+ device. When used with the HIMIB chip, this pin must be pulled up via a high-value resistor.
RXD+0-7, RXD-0-7
Receive Data Input 10BASE-T port differential receive inputs (8 ports).
SCLK
Serial Clock Input In normal operating mode, serial data (input or output) is clocked (in or out) on the rising edge of the signal on this pin. SCLK is asynchronous to X1 and can operate up to 10 MHz. In Minimum mode, this pin, together with the SI pin, controls which information is output on the SO pin.
TEST
Test Pin Input, Active HIGH This pin should be tied LOW for normal operation. If this pin is driven HIGH, then the IMR+ device can be programmed for Loopback Test mode. Also, if this pin is HIGH when the RST pin is deasserted, the IMR+ device will enter the Minimum mode. An inverted version of the RST signal can be used to program the device into the Minimum mode.
Test 0 0 1 1 SI 0 1 0 1 Functions Normal Management Mode Normal Management Mode Minimum Mode, Receive Polarity Correction Disabled Minimum Mode, Receive Polarity Correction Enabled
SI
Serial In Input In normal operating mode, the SI pin is used for test/ management serial input port. Management commands are clocked in on this pin synchronous to the SCLK input. In Minimum mode, this pin, together with the SCLK pin, controls which information is output on the SO pin. In Minimum mode, the state of SI at the deassertion of RST signal determines the programming of automatic polarity detection/correction for 10BASE-T ports.
SO
Serial Out Output In normal operating mode, the SO pin is used for test/ management serial output port. Management results are clocked out on this pin synchronous to the SCLK
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TXD+0-7, TXD-0-7
Transmit Data Output 10BASE-T port differential drivers (8 ports).
X1
Crystal 1 Crystal Connection The internal clock generator uses a 20 MHz crystal attached to pins X1 and X2. Alternatively, an external 20MHz CMOS clock signal can be used to drive this pin.
TXP+0-7, TXP-0-7
Transmit Predistortion Output 10BASE-T transmit waveform predistortion control differential outputs (8 ports).
X2
Crystal 2 Crystal Connection The internal clock generator uses a 20 MHz crystal attached to pins X1 and X2. If an external clock source is used, this pin should be left unconnected.
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FUNCTIONAL DESCRIPTION
The AM79C981 Integrated Multiport Repeater Plus device is a single chip implementation of an IEEE 802.3/Ethernet repeater (or hub). In addition to the eight integral 10BASE-T ports plus one AUI port comprising the basic repeater, the IMR+ chip also provides the hooks necessary for complex network management and diagnostics. The IMR+ device is also expandable, enabling the implementation of high port count repeaters based on several IMR+ devices. The IMR+ device interfaces directly with AMD's Am79C987 Hardware Implemented Management Information Base (HIMIB) device to allow a fully managed multiport repeater to be implemented as specified by the Layer Management for 10 Mb/s Baseband Repeaters Standard. When the IMR+ and HIMIB devices are used as a chip set, the HIMIB device maintains complete repeater and per port statistics which can be accessed on demand by a microprocessor through a simple 8-bit parallel port. The IMR+ chip complies with the full set of repeater basic functions as defined in section 9 of ISO 8802.3 (ANSI/IEEE 802.3c). These functions are summarized below.
IMR+ chip can be read through the Management Port using the Get MJLP Status command (M bit returned).
Collision Handling
The IMR+ chip will detect and respond to collision conditions as specified in 802.3. A multiple-IMR+ device repeater implementation also complies with the 802.3 specification due to the inter-IMR+ chip status communication provided by the expansion port. Specifically, a repeater based on one or more IMR+ devices will handle the transmit collision and one-port-left collision conditions correctly as specified in Section 9 of the 802.3 specification.
Fragment Extension
If the total packet length received by the IMR+ device is less than 96 bits, including preamble, the IMR+ chip will extend the repeated packet length to 96 bits by appending a Jam sequence to the original fragment.
Auto Partitioning/Reconnection
Any of the integral TP ports and AUI port can be partitioned under excessive duration or frequency of collision conditions. Once partitioned, the IMR+ device will continue to transmit data packets to a partitioned port, but will not respond (as a repeater) to activity on the partitioned port's receiver. The IMR+ chip will monitor the port and reconnect it once certain criteria indicating port `wellness' are met. The criteria for reconnection are specified by the 802.3 standard. In addition to the standard reconnection algorithm, the IMR+ device implements an alternative reconnection algorithm which provides a more robust partitioning function for the TP ports and/or the AUI port. Each TP port and the AUI port are partitioned and/or reconnected separately and independently of other network ports. Either one of the following conditions occuring on any enabled IMR+ device network port will cause the port to partition: a. A collision condition exists continuously for a time between 1024- to 2048-bit times (AUI port--SQE signal active; TP port--simultaneous transmit and receive) b. A collision condition occurs during each of 32 consecutive attempts to transmit to that port. Once a network port is partitioned, the IMR+ device will reconnect that port if the following is met: a. Standard reconnection algorithm--A data packet longer than 512-bit times (nominal) is transmitted or received by the partitioned port without a collision. b. Alternate reconnection algorithm--A data packet longer than 512-bit times (nominal) is transmitted by the partitioned port without a collision.
Repeater Function
If any single network port senses the start of a valid packet on its receive lines, then the IMR+ device will retransmit the received data to all other enabled network ports. The repeated data will also be presented on the DAT line to facilitate multiple-IMR+ device repeater applications.
Signal Regeneration
When re-transmitting a packet, the IMR+ device ensures that the outgoing packet complies with the 802.3 specification in terms of preamble structure, voltage amplitude, and timing characteristics. Specifically, data packets repeated by the IMR+ chip will contain a minimum of 56 preamble bits before the Start of Frame Delimiter. In addition, the voltage amplitude of the repeated packet waveform will be restored to levels specified in the 802.3 specification. Finally, signal symmetry is restored to data packets repeated by the IMR+ device, removing jitter and distortion caused by the network cabling.
Jabber Lockup Protection
The IMR+ chip implements a built-in jabber protection scheme to ensure that the network is not disabled due to transmission of excessively long data packets. This protection scheme will automatically interrupt the transmitter circuits of the IMR+ device for 96-bit times if the IMR+ device has been transmitting continuously for more than 65,536-bit times. This is referred to as MAU Jabber Lockup Protection (MJLP). The MJLP status for the
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PRELIMINARY to be repeated with correct polarity. This function is executed once following reset or link fail, and has a programmable enable/disable option on a port-by-port basis. This function is disabled upon reset and can be enabled via the IMR+ chip Management Port.
The reconnection algorithm option (standard or alternate) is a global function for the TP ports, i.e. all TP ports use the same reconnection algorithm. The AUI reconnection algorithm option is programmed independently of the TP port reconnection option.
Link Test
The integral TP ports implement the Link Test function as specified in the 802.3 10BASE-T standard. The IMR+ device will transmit Link Test pulses to any TP port after that port's transmitter has been inactive for more than 8 to 17 ms. Conversely, if a TP port does not receive any data packets or Link Test pulses for more than 65 to 132 ms and the Link Test function is enabled for that port then that port will enter link fail state. A port in link fail state will be disabled by the IMR+ chip (repeater transmit and receive functions disabled) until it receives either four consecutive Link Test pulses or a data packet. The Link Test receive function itself can be disabled via the IMR+ chip management port on a port-by-port basis to allow the IMR+ device to interoperate with pre10BASE-T twisted pair networks that do not implement the Link Test function. This interoperability is possible because the IMR+ device will not allow the TP port to enter link fail state, even if no Link Test pulses or data packets are being received. Note however that the IMR+ chip will always transmit Link Test pulses to all TP ports regardless of whether or not the port is enabled, partitioned, in link fail state, or has its Link Test receive function disabled.
Reset
The IMR+ device enters reset state when the RST pin is driven LOW. After the initial application of power, the RST pin must be held LOW for a minimum of 150 s (3000 X1 clock cycles). If the RST pin is subsequently asserted while power is maintained to the IMR+ device, a reset duration of only 4 s is required. The IMR+ chip continues to be in the reset state for 10 X1 clocks (0.5 s) following the rising edge of RST. During reset, the output signals are placed in their inactive states. This means that all analog signals are placed in their idle states, bidirectional signals (except STR signal) are not driven, active LOW signals are driven HIGH, and all active HIGH signals and the STR pin are driven LOW. An internal circuit ensures that a minimum reset pulse is generated for all internal circuits. For a RST input with a slow rising edge, the input buffer threshold may be crossed several times due to ripple on the input waveform. In a multiple IMR+ chip repeater the RST signal should be applied simultaneously to all IMR+ devices and should be synchronized to the external X1 clock. Reset synchronization is also required when accessing the PAM (Port Activity Monitor). The SI signal should be held HIGH for at least 500 ns following the rising edge of RST. Table 1 summarizes the state of the IMR+ chip following reset.
Polarity Reversal
The TP ports have the optional (programmable) ability to invert (correct) the polarity of the received data if the TP port senses that the received data packet waveform polarity is reversed due to a wiring error. This receive circuitry polarity correction allows subsequent packets
Table 1. IMR+ Chip After Reset
Function Active LOW outputs Active HIGH outputs SO Output DAT, JAM STR Transmitters (TP and AUI) Receivers (TP and AUI) AUI Partitioning/Reconnection Algorithm TP Port Partitioning/Reconnection Algorithm Link Test Function for TP Ports Automatic Receiver Polarity Reversal Function HIGH LOW HIGH HI-IMPEDANCE LOW IDLE ENABLED STANDARD ALGORITHM STANDARD ALGORITHM ENABLED, TP PORTS IN LINK FAIL DISABLED State After Reset Pull Up/Pull Down No No No Either Pull Up* No Terminated N/A N/A N/A N/A
*Only when used with the HIMIB device.
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Expansion Port
The IMR+ chip Expansion Port is comprised of five pins; two are bi-directional signals (DAT and JAM), two are input signals (ACK and COL), and one is an output signal (REQ). These signals are used when a multiple-IMR+ device repeater application is employed. In this configuration, all IMR+ chips must be clocked synchronously with a common clock connected to the X1 inputs of all IMR+ devices. Reset needs to be synchronized to X1 clock. The IMR+ device expansion scheme allows the use of multiple IMR+ chips in a single board repeater or a modular multiport repeater with a backplane architecture. The DAT pin is a bidirectional I/O pin which can be used to transfer data between the IMR+ devices in a multiple-IMR+ chip design. The data sent over the DAT line is in NRZ format and is synchronized to the common clock. The JAM pin is another bidirectional I/O pin that is used by the active IMR+ chip to communicate its internal status to the remaining (inactive) IMR+ devices. When JAM is asserted HIGH, it indicates that the active IMR+ device has detected a collision condition and is generating Jam Sequence. During this time when JAM is asserted HIGH, the DAT line is used to indicate whether the active IMR+ chip is detecting collision on one port only or on more than one port. When DAT is driven HIGH by the IMR+ chip (while JAM is asserted by the IMR+ chip), then the active IMR+ device is detecting a collision condition on one port only. This `one-port-left' signaling is necessary for a multiple-IMR+ device repeater to function correctly as a single multiport repeater unit. The IMR+ chip also signals the `one port left' collision condition in the event of a runt packet or collision fragment; this signal will continue for one expansion port bus cycle (100 ns) before deasserting REQ. The arbitration for access to the bussed bi-directional signals (DAT and JAM) is provided by one output (REQ) and two inputs (ACK and COL). The IMR+ chip asserts the REQ pin to indicate that it is active and wishes to drive the DAT and JAM pins. An external arbiter senses the REQ lines from all the IMR+ devices and asserts the ACK line when one and only one IMR+ chip is asserting its REQ line. If more than one IMR+ chip is asserting its REQ line, the arbiter must assert the COL signal, indicating that more than one IMR+ device is active. More
than one active IMR+ device at a time constitutes a collision condition, and all IMR+ devices are notified of this occurence via the COL line of the Expansion Port. Note that a transition from multiple IMR+ devices arbitrating for the DAT and JAM pins (with COL asserted, ACK deasserted) to a condition when only one IMR+ chip is arbitrating for the DAT and JAM pins (with ACK asserted, COL deasserted) involves one expansion port bus cycle (100 ns). During this transitional bus cycle, COL is deasserted, ACK is asserted, and the DAT and JAM pins are not driven. However, each IMR+ device will remain in the collision state (transmitting jam sequence) during this transitional bus cycle. In subsequent expansion port bus cycles (REQ and ACK still asserted), the IMR+ devices will return to the `master and slaves' condition where only one IMR+ device is active (with collision) and is driving the DAT and JAM pins. An understanding of this sequence is crucial if nonIMR+ devices (such as an Ethernet controller) are connected to the expansion bus. Specifically, the last device to back off of the Expansion Port after a multiIMR+ chip collision must assert the JAM line until it too drops its request for the Expansion Port.
External Arbiter
A simple arbitration scheme is required when multiple IMR+ devices are connected together to increase the total number of repeater ports. The arbiter should have one input (REQ1...REQn) for each of the n IMR+ devices to be used, and two global outputs (COL and ACK). This function is easily implemented in a PAL(R) device, with the following logic equations:
ACK = + REQ1 & REQ2 & REQ3 & ....REQn REQ1 & REQ2 & REQ3 & ....REQn
* * *
+ COL =
REQ1 & REQ2 & REQ3 & .... REQn ACK & (REQ1 + REQ2 + REQ3 + ... REQn)
Above equations are in positive logic, i.e., a variable is true when asserted. A single PALCE16V8 will perform the arbitration function for a repeater based on several IMR+ devices.
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REQ2 REQ3 REQ1 COL ARBITER ACK ACK REQ
Bus transceivers needed if DAT and JAM buses exceed 100 pF loading.
DIR 1/2 '74 ASYNC RESET DD FF Q CK ACK REQ DAT A B Note 1
COL AM79C981 RST IMR+ Chip X1
1
JAM
XTAL OSC.
ACK
REQ
DAT JAM
COL AM79C981 RST IMR+ Chip X1
2
ACK
REQ DAT
COL AM79C981 RST
Note 1: Direction BA AB DIR LOW HIGH
IMR+ Chip 3
JAM
X1
17306B-5
Figure 1. Multiple IMR+ Devices
Modular Repeater Design
The expansion port of the IMR+ chip also allows for modular expansion. By sharing the arbitration duties between a backplane bus architecture and several separate repeater modules one can build an expandable repeater based on modular `plug-in' cards. Each
repeater module performs the local arbitration function for the IMR+ devices on that module, and provides signals to the backplane for use by a global arbiter. For more detailed information, see AMD's IEEE 802.3 Repeater Technical Manual, PID# 17314A.
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Repeater MAC Interconnection
Because all repeated data in the IMR+ chip or multiIMR+ chip design is available on the Expansion Port, all network traffic can be monitored by an external Media Access Controller (MAC) device such as the Am7990, Am79C900, Am79C940, or Am79C960. A repeater with such a controller is capable of providing extensive hub management functions, as well as being addressable as a network node. The MAC device can gather statistics and data concerning the state of the hub and the
network, and the network addressability allows a remote management station to monitor this statistical data and to request actions to be performed by the repeater (i.e. port enable/disable). Figure 2 shows how to interface a repeater based on multiple IMR+ devices to an Ethernet controller such as the Am79C900 ILACC or the Am7990 LANCE. For more information on this design, refer to AMD's IEEE 802.3 Repeater Technical Manual, PID# 17314A.
RENA
RXD
RXC
CDT
COLCLK ACKCLK
RTSCLK
RTS
XCOL
CRS SYNC DATA RXC ACK IMR+n COL ACK
RTS
Q0 Q1 Q2 Q3 Q4
DONE_COUNT NEW96 TCK Counter PALCE22V10 20MHz RESET
DONE_COUNT NEW96
RTS
Arbiter PALCE16V8
CDT REQn
Interface PALCE16V8 RTSCLK CDT RCKEN ACKCLK DAT JAM TCK REQ
17306B-6
ARST
REQ1
REQ2
Q5 Q6
TCK TCK
COL
ARST
REQ
DAT
JAM
ACK
REQ
ACK
ACK
DAT
DAT
COL
COL
JAM
JAM
DAT
IMR+1 X1 RST X1
IMR+2 RST X1
JAM
RST
20 MHz Osc.
14396C-033A
Figure 2. Expandable Modular Repeater AM79C981 1-83
TCK
TXD
TXD
TxC
Am7990 LANCE Am79C900 ILACC Am79C940 MACE or Am79C960 PCnet-ISA
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PRELIMINARY setup and hold times with respect to the input bit pattern. If the latter method is used, it is to be noted that 20 SCLK clock transitions are required for proper execution of management commands that produce SO data, and that 14 SCLK clock transitions are needed to execute management commands that do not produce SO data.
Management Port
The IMR+ device management functions are enabled when the TEST pin is tied LOW. The management commands are byte oriented data and are input serially on the SI pin. Any responses generated during execution of a management command are output serially in a byteoriented format by the IMR+ device on the SO pin. Both the input and output data streams are clocked with the rising edge of the SCLK pin. The serial command data stream and any associated results data stream are structured in a manner similar to the RS232 serial data format, i.e., one Start Bit followed by eight Data Bits. The externally generated clock at the SCLK pin can be either a free running clock synchronized to the input bit patterns or a series of individual transitions meeting the
Command Execution Phase
Management Commands
The following section details the operation of each management command available in the IMR+ chip. In all cases, the individual bits in each command byte are shown with the MSB on the left and the LSB on the right. Data bytes are received and transmitted LSB first and MSB last. See Table 2 for a summary of the management commands.
Results Phase
Next Command
SCLK
SI
STRT D0 D1 D2 D3 D4 D5 D6 D7
SO
STRT D0 D1 D2 D3 D4 D5 D6 D7 17306B-17
Management Command/Response Timing
Command Execution Phase
Next Command Execution Phase
SCLK
SI
STRT D0 D1 D2 D3 D4 D5 D6 D7 STRT D0 D1 D2 D3 D4 D5 D6 D7 17306B-18
SO
Management Command Timing with No Response
1-84
AM79C981
PRELIMINARY Table 2. Management Port Command Summary
Commands Set (Write) Opcodes IMR+ Chip Programmable Options Alternate AUI Partitioning Algorithm Alternate TP Partitioning Algorithm AUI Port Disable AUI Port Enable TP Port Disable TP Port Enable Disable Link Test Function (per TP port) Enable Link Test Function (per TP port) Disable Automatic Receiver Polarity Reversal (per TP port) Enable Automatic Receiver Polarity Reversal (per TP port) Get (Read) Opcodes AUI Port Status (B, S, L Cleared) TP Port Partitioning Status Bit Rate Status of TP ports Link Test Status of TP ports Receive Polarity Status of all TP ports MJLP Status Version AUI Port Status (S, L Cleared) AUI Port Status (B Cleared) AUI Port Status (None Cleared) 1000 1111 1000 0000 1010 0000 1101 0000 1110 0000 1111 0000 1111 1111 1000 1011 1000 1101 1000 1001 PBSL 0000 C7...C0 E7...E0 L7...L0 P7...P0 M000 0000 XXXX 0001 PBSL 0000 PBSL 0000 PBSL 0000 0000 1CSA 0001 1111 0001 0000 0010 1111 0011 1111 0010 0### 0011 0### 0100 0### 0101 0### 0110 0### 0111 0### SI Data SO Data
AMD
Notes: 1. Unused opcodes are reserved for future use. 2. ### is the port number (000 to 111 for TP0 to TP7)
AM79C981
1-85
AMD
PRELIMINARY A--Alternative Port Activity Monitor (PAM) Function Setting the Alternative Port Activity Monitor Function allows the PAM function to be altered such that the Carrier Sense data is presented unmodified. In default operation the PAM output (Carrier Sense bits in the CRS bit stream) are masked if the port is either disabled or partitioned. This does not allow the Repeater Management software to sense activity on all segments at all times. The ability to monitor partitioned or disabled ports allows fault tolerance to be built into the Repeater Management software. Alternate AUI Port Partitioning Algorithm
SET (Write) Opcodes
IMR+ Chip Programmable Options SI data: SO data: 0000 1CSA None
IMR+ Chip Programmable Options can be enabled (disabled) by setting (resetting) the appropriate bit in the command string. The three programmable bits are: C--CI Reporting; S--AUI SQE Test Mask, and A--Alternative Port Activity Monitor (PAM) Function. These options can be enabled (disabled) by setting (resetting) the appropriate bit in the command string. When writing to this register through the Am79C987 HIMIB device, the A and C bits should not be changed (A=0, C=1). C--CI Reporting Setting this bit alters the function of the STR pin. In this mode, the STR pin becomes an input in response to the AMD's Am79C987 HIMIB device. Upon deassertion of RST, the HIMIB automatically sets this bit following IMR/ IMR+ device type detection. When this mode is selected, the CRS output bit string format is modified to include CI carrier bit (in addition to AUI carrier). This bit occupies the bit position immediately preceding the AUI bit in the CRS bit string (10 bits) output. Note that the AUI bit gets asserted if either the CI or DI signal pairs are active. S--AUI SQE Test Mask Setting this bit allows the IMR+ chip to ignore activity on the CI signal pair, in the SQE Test Window, following a transmission on the AUI port. This event occurs when the attached MAU has the SQE Test option enabled, therefore generating a burst of CI activity following every transmission. This is interpreted by the IMR+ device as a collision, causing the IMR+ device to generate a full Jam pattern. Although the MAU attached to a repeater is required not to have its SQE test function active, this is a common installation error, causing difficulty in diagnosing network throughput problems. The SQE Test Window, as defined by the IEEE 802.3 (Section 7.2.2.2.4), is from 6-bit times to 34-bit times (0.6 s to 3.4 s). This includes delay introduced by a 50 m AUI. CI activity that occurs outside this window is not ignored and is treated as true collision. Note that enabling this function does not prevent the reporting of this condition by the IMR+ device and the two functions operate independently.
SI data: SO data:
00011111 None
The AUI port Partitioning/Reconnection scheme can be programmed for the alternate (transmit only) reconnection algorithm by invoking this command. To return the AUI back to the standard (transmit or receive) reconnection algorithm, it is necessary to reset the IMR+ device. Standard partitioning algorithm is selected upon reset. Alternate TP Ports Partitioning Algorithm SI data: SO data: 00010000 None
The TP ports Partitioning/Reconnection scheme can be programmed for the alternate (transmit only) reconnection algorithm by invoking this command. All TP ports are affected as a group by this command. To return the TP ports back to the standard (transmit or receive) reconnection algorithm, it is necessary to reset the IMR+ device. The standard partitioning algorithm is selected upon reset. AUI Port Disable SI data: SO data: 00101111 None
The AUI port will be disabled upon receiving this command. Subsequently, the IMR+ chip will ignore all inputs (Carrier Sense and SQE) appearing at the AUI port and will not transmit any data or Jam Sequence on the AUI port. Issuing this command will also cause the AUI port to have its internal partitioning state machine forced to its idle state. Therefore, a Partitioned Port may be reconnected by first disabling and then re-enabling the port.
1-86
AM79C981
PRELIMINARY AUI Port Enable SI data: SO data: 00111111 None Enable Link Test Function of a TP Port SI data: SO data: 01010### None
AMD
This command enables a previously disabled AUI port. Note that a partitioned AUI port may be reconnected by first disabling (AUI Port Disable Command) and then reenabling the port with this command. All ports are enabled upon reset. TP Port Disable SI data: SO data: 00100### None
(### is TP port number) This command re-enables the Link Test Function in the TP port designated in the command byte. This command executes only if the designated TP port has had the Link Test Function disabled by the Disable Link Test Function command. Otherwise, the command is ignored. Link Test is enabled upon reset. Disable Automatic Receiver Polarity Reversal SI data: SO data: 01100### None
(### is TP port number) The TP port designated in the command byte will be disabled upon receiving this command. Subsequently, the IMR+ device will ignore all inputs appearing at the disabled port's receive pins and will not transmit any data or JAM Sequence on that port's transmit pins. Issuing this command will also cause a TP port to have its partitioning state machine returned to its Idle State (Port Reconnected). Therefore, a partitioned port may be reconnected by first disabling and then re-enabling the port. The disabled port will continue to report correct Link Test Status. TP Port Enable SI data: SO data: 00110### None
(### is TP port number) This command disables the Automatic Receiver Polarity Reversal Function for the TP port designated in the command byte. If this function is disabled on a TP port with reverse polarity (due to a wiring error), then the TP port will fail Link Test due to the reversed polarity of the Link Pulses. If the Link Test Function is also disabled on the TP port, then the received reversed polarity packets would be repeated to all other network ports in the IMR+ chip as inverted data. Automatic Polarity reversal is disabled upon reset. Enable Automatic Receiver Polarity Reversal SI data: SO data: 01110### None
(### is TP port number) This command enables a previously disabled TP port. Re-enabling a disabled port causes the port to be placed into Link Test Fail state. This ensures that packet fragments received on the port are not repeated to the rest of the network. Note that to force a TP port into the Link Fail state and/or to reconnect a partitioned TP port, the port should first be disabled (TP Port Disable Command) and then re-enabled with this command. All ports are enabled upon reset. Disable Link Test Function of a TP Port SI data: SO data: 01000### None
(### is TP port number) This command enables the Automatic Receiver Polarity Reversal Function for the TP port designated in the command byte. If enabled in a TP port, the IMR+ chip will automatically invert the polarity of that TP port's receiver circuitry if the TP port is detected as having reversed polarity (due to a wiring error). After reversing the receiver polarity, the TP port could then receive subsequent (reverse polarity) packets correctly.
GET (Read) Opcodes
AUI Port Status SI data: SO data: 10001111 PBSL0000
(### is TP port number) This command disables the Link Test Function at the TP port designated in the command byte, i.e., the TP port will no longer be disconnected due to Link Fail. A TP port which has its Link Test Function disabled will continue to transmit Link Test Pulses. If a twisted pair port has Link Test disabled, then reading the Link Test Status indicates it being in Link Test Pass.
The combined AUI status allows a single instruction to be used for monitoring AUI port. The four status bits reported are:
AM79C981
1-87
AMD
PRELIMINARY Bit Rate Error Status of TP Ports SI data: SO data: 10100000 E7...............E0
P Partitioning Status. This bit is 0 if the AUI port is partitioned and 1 if connected. B Bit Rate Error. This bit is set to 1 if there has been an instance of FIFO Overflow or Underflow, caused by data received at the AUI port. This bit is cleared when the status is read. S SQE Test Status. This bit is set to 1 if SQE Test is detected by the IMR+ chip. This bit is cleared when the status is read. A MAU attached to a repeater must have SQE Test disabled. This bit is set even if the AUI port is disabled or partitioned. L Loop Back Error. The MAU attached to the AUI is required to loopback data transmitted to DO onto the DI circuit. If loopback carrier is not detected by the IMR+ device, then this bit is set to 1 to report this condition. This bit is cleared when the status is read. For a repeater this is the only indication of a broken or missing MAU. Alternate AUI Port Status SI data: SO data: 10001111 PBSL0000
This allows a single command to be used to report Bit Rate Error condition (FIFO Overflow or Underflow) of all Twisted Pair ports. The 8 bits of the output pattern correspond to each of the 8 TP ports, with least significant bit corresponding to port 0. The status bit for a port is set to 1 if there has been an instance when data received from that port has caused a FIFO error. All status bits stay set until the status is read. Link Test Status of TP Ports SI data: SO data: Ln = 0 Ln = 1 11010000 L7...............L0 TP Port n in Link Test Fail TP Port n in Link Test Pass
There are three further variations of the above command, allowing selective clearing of a combination of B, S, and L bits. They are primarily included for use by the HIMIB chip. These are: Alternative 1. SI data: SO data: 10001011 PBSL0000
The Link Test Status of all eight TP ports are accessed by this command. A disabled port continues to report correct Link Test Status. Re-enabling a disabled port causes the port to be placed into Link Test Fail state. This ensures that packet fragments received on the port are not repeated to the rest of the network. Receive Polarity Status of TP Ports SI data: SO data: Pn = 0 Pn = 1 11100000 P7...............P0 TP Port n Polarity Correct TP Port n Polarity Reversed
B is not cleared. S and L are cleared. Alternative 2. SI data: SO data: 10001101 PBSL0000
S and L are not cleared. B is cleared. Alternative 3. SI data: SO data: 10001001 PBSL0000
The statuses of all eight TP port polarities are accessed with this command. The IMR+ chip has the ability to detect and correct reversed polarity on the TP ports' RXD+/- pins. If the polarity is detected as reversed for a TP port, then the IMR+ chip will set the appropriate bit in this command's result byte only if the Polarity Reversal Function is enabled for that port. MJLP Status SI data: SO data: 11110000 M00000000
None of S, B and L are cleared. TP Port Partitioning Status SI data: SO data: Pn = 0 Pn = 1 10000000 P7.................P0 TP port n partitioned TP port n connected
The partitioning Status of all eight TP ports are accessed by this command. If a port is disabled, reading it partitioning status will indicate that it is connected.
Each IMR+ chip contains an independent MAU Jabber Lock Up Protection Timer. The timer is designed to inhibit the IMR+ device transmit function, if it has been transmitting continuously for more than 65536 Bit Times. The MJLP Status bit (M) is set to 1 if this happens. This bit remains set and is only cleared when the MJLP status is read by using this command.
1-88
AM79C981
PRELIMINARY Version SI data: SO data: 11111111 XXXX0001
AMD
In Minimum Mode, the SO pin is used to serially output the various status information based on the state of the SI and SCLK pins. A summary of the status information is provided in the following table.
SCLK 0 0 1 1 SI 0 1 0 1 SO Output TP Ports Receive Polarity Status + AUI SQE Test Error Status. Bit Rate Error (all ports). TP Ports Link Status + AUI LoopBack Status Port Partitioning Status (all ports)
This command (1111 1111) can be used to determine the device version. The IMR+ chip responds by the bit pattern: XXXX 0001 The IMR chip (Am79C980) responds by the bit pattern: XXXX 0000
Minimum Mode
The Minimum Mode reconfigures the IMR+ device Management Port and is intended to provide support for the low end, non-managed repeaters, requiring minimal external logic to provide LED indication of:
s Twisted Pair Ports Link Status indication and AUI
When SI = 0 then SO will output the related AUI status bits (LoopBack or SQE), followed by the 8 TP status bits (Link or Polarity), starting with the TP port 0. When SI = 1, the Port Partitioning Status or Port Bit Rate Error Status are scanned out with the AUI first and TP ports following. TP Port 0 is scanned out first.
Loopback Status
s Port Partitioning Status s Twisted Pair Ports Receiver Polarity Status and
AUI SQE Test Error Status
s Port Bit Rate Error Status
The Minimum Mode is selected by controlling the state of the TEST pin while RST is asserted. If TEST is High (asserted), while reset is active (RST LOW), then Minimum Mode is selected. The state of SI pin, at the deassertion of the RST signal, determines whether the IMR+ chip is to be programmed for Automatic Polarity Detection/Correction. When entering the Minimum Mode, the TEST input has to be deasserted on the rising edge of reset. A maximum delay of 100 ns is allowed to account for slow devices. The following table summarizes the different modes available.
Test 0 0 1 1 SI 0 1 0 1 Functions Normal Management Mode Normal Management Mode Minimum Mode, Receive Polarity Correction disabled Minimum Mode, Receive Polarity Correction enabled
Note that the Bit Rate Error, AUI Loopback, and AUI SQE Test Error status bits stay set until they are scanned out.
The state of SI and SCLK inputs is checked at the end of every STR cycle. The rising edge of the X1 clock, occurring before falling edge of STR, is used to strobe in the state of the SI and SCLK pins. In this Minimum Mode, the Management Port mode is not active. To exit the Minimum mode, the IMR+ device must reset into the normal Management Port mode.
AM79C981
1-89
AMD
PRELIMINARY
1/2 '74 D Q TCK TCK
CK Q CLR
XTAL OSC
X1 SO X2
CK SI
SIPO
1/2 '74 CK ASYNC RESET D Q RST TEST
AM79C981 IMR+ Chip
STR CK Register
SCLK
SI
TTT PPP 765
TA PU 0I
17306B-7
Figure 3. Minimum Mode, Non-Intelligent Repeater Example
X1
TCK (Note 1) CRS AUI CRS TP0 CRS TP1 CRS TP2 CRS TP3 CRS TP4 CRS TP5 CRS TP6 CRS TP7 CRS AUI
CRS (Note 2)
SO (Note 3)
SO AUI
SO TP0
SO TP1
SO TP2
SO TP3
SO TP4
SO TP5
SO TP6
SO TP7
SO AUI
STR
Notes: 1. Externally generated signal illustrates internal IMR+ chip clock phase relationship. 2. CRS timing with the C-bit cleared (IMR+ Chip Programmable Options) 3. For Minimum Hub Mode
17306B-8
Figure 4. Management Port Minimum Mode and Port Activity Monitor Signal Relationship
Port Activity Monitor
Two pins, CRS and STR, are used to serially output the state of the internal Carrier Sense signals from the AUI and the eight TP ports. This function together with external hardware and/or software can be used to monitor repeater receive and/or collision activity.
The following diagram shows typical external hardware employed to convert the serial bit stream into parallel form. The accuracy of the CRS signals is 10 Bit Times (BT) (1 s). Specifically, a transition to active state by any of the internal carrier sense bits that lasts for less than 10BT is latched internally and is used to set the appropriate bit during the next sample period.
1-90
AM79C981
PRELIMINARY
1/2 '74 D Q TCK TCK
AMD
CK Q CLR
XTAL OSC
Shift Register X1 CRS X2 CK SI SIPO
1/2 '74 CK ASYNC RESET D Q RST
AM79C981 IMR+ Chip
STR CK Register
TTT PPP 765
TA PU 0I
Carrier Sense Outputs
17306B-9
Figure 5a. Port Activity Monitor Implementation
1 X1
2
9
10
11
RST
TCK (Note 1)
CRS
AUI
TP0
TP1
TP7
X (Note 2)
AUI
TP0
STR (Note 3)
Notes: 1. Externally generated signal illustrates internal IMR+ chip clock phase relationship. 2. IMR+ chip standalone, X will be low. When attached to a HIMIB device, X reflects the state of the CI pair. 3. STR signal is not available when the IMR+ chip is attached to HIMIB device, and must be generated externally.
17306B-10
Figure 5b. Port Activity Monitor Implementation (Continued)
AM79C981
1-91
AMD
PRELIMINARY TXP outputs. Only receive data that passes the required amplitude squelch criteria is looped back to the transmit outputs. Note that the data is looped back unaltered, meaning that no signal retiming or regeneration takes place. Therefore, any signal distortion present on the receive data paths will be retransmitted. In Minimum Mode, the Loopback Test Mode cannot be accessed. The IMR+ device will return to normal operation when the TEST pin is again driven LOW.
Loopback Test Mode
The IMR+ chip can be programmed to enter Loopback Mode on all network ports. This is accomplished by first driving the TEST pin HIGH, then clocking (using the SCLK pin) a minimum of three 0s into the SI pin. This causes the IMR+ chip to loop all received data on each port back to each port's corresponding transmit outputs. Specifically, the AUI DI input is passed unaltered to the AUI DO output, and each RXD input on the twisted pair ports is passed (unaltered) to the respective TXD and
TEST
SI
SCLK
17306B-11
Figure 6. Programming the IMR+ Device for Loopback Mode
1-92
AM79C981
PRELIMINARY
AMD
IMR+ Chip External Components
Figure 6 shows a typical twisted pair port external components schematic. The resistors used should have a 1% tolerance to ensure interoperability with 10BASE-T compliant networks. The filters and pulse transformers are necessary devices that have a major influence on the performance and compliance of the 10BASE-T ports of the repeater. Specifically, the transmitted waveforms are heavily influenced by the filter characteristics and
the twisted pair receivers employ several criteria to continuously monitor the incoming signal's amplitude and timing characteristics to determine when and if to assert the internal carrier sense. For these reasons, it is crucial that the values and tolerances of the external components be as specified. Several manufacturers produce a module that combines the functions of the transmit and receive filters and the pulse transformers into one package.
Filter & Transformer Module 1:1
1.21K
TXD+ TXP+ AM79C981 TXD- TXP- RXD+ RXD-
61.9 422 61.9 422
RJ45 Connector
TD+ TD- 3 6
XMT Filter Note 1 RCV Filter 1:1
Note 2
100
RD+ 1 RD- 2
17306B-12 Notes: 1. Compatible filter modules, with a brief description of package type and features are included in the Appendix.
2. The resistor values are recommended for general purpose use and should allow compliance to the 10BASE-T specification for template fit and jitter performance. However, the overall performance of the transmitter is also affected by the transmit filter configuration.
Figure 7a. Typical TP Port External Components
Pulse Transformer DO+ DO- AM79C981 DI+ DI- CI+ CI-
40.2 40.2
AUI Connector
3
Note 1
10 5 12 2 9
40.2
40.2
0.1F Optional ANLG GND
0.1F
17306B-13
Notes: 1. Compatible AUI transformer modules, with a brief description of package type and features are included in the Appendix. 2. The differential input DI and the CI pairs are externally terminated by two 40.2 1% resistors and one optional commonmode bypass capacitor. The differential input impedance, ZIDF, and the common-mode input impedance, ZICM, are specified so that the Ethernet specification for cable termination impedance is met using standard 1% resistor terminators. If SIP devices are used, 39 is the nearest usable equivalent value.
Figure 7b. Typical AUI Port Components AM79C981 1-93
AMD
PRELIMINARY
APPLICATIONS
A fully managed multiport repeater can be easily built by interfacing the IMR+ chip with the Hardware Implemented Management Information Base (HIMIB), Am79C987 device. The HIMIB device interfaces with all common Microprocessor System Busses with a
Host System Bus
minimum of external logic. Note that additional buffering of DAT and JAM are required for most applications. For more information, refer to AMD's IEEE 802.3 Repeater Technical Manual (PID# 17314A).
Expansion Bus
Address Decode
CS HIMIB C/D
DAT JAM
CRS STR SI SO SCLK
Data Buffer
D [7-0] RD WR RDY INT ACK COL RST CK
CRS STR SI IMR+ SO SCLK X1 REQ
17306B-14
Figure 8. Simplified ISA-HUB Block Diagram
1-94
AM79C981
PRELIMINARY
AMD
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature Under Bias . . . . . . . 0 to 70C Supply Voltage referenced to AVSS or DVSS (AVDD, DVDD) . . . . . . . . . . -0.3 to +6 V
Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices Temperature (TA) . . . . . . . . . . . . . . . . 0 to +70C Supply Voltage (AVDD, DVDD) . . . . . . . 5 V to 5%
Operating ranges define those limits between which the funtionality of the device is guaranteed .
DC CHARACTERISTICS over operating ranges unless otherwise specified
Parameter Symbol Digital I/O VIL VIH VOL VOH IIL VILX VIHX IILX IIHX AUI Port IIAXD VAICM VAIDV VASQ VATH VAOD VAODI VAODOFF IAODOFF VAOCM Input Current at DI+/and CI+/- pairs DI+,DI-,CI+,CI- Open Circuit Input Common Mode Voltage (bias) Differential Mode Input Voltage Range (DI, CI) DI, CI Squelch Threshold DI Switching Threshold Differential Output Voltage |(DO+) - (DO-)| DO Differential Output Voltage Imbalance DO Differential Idle Output Voltage DO Differential Idle Output Current DO+/- Common Mode Output Voltage (Note 1) RL = 78 RL = 78 RL = 78 RL = 78 (Note 1) RL = 78 AVSS < VIN < AVDD IIN = 0A, AVSS = 0 V AVDD = 5.0 V -500 AVDD - 3.0 -2.5 -275 -35 620 -25 -40 -1 2.5 +500 AVDD-1.0 +2.5 -160 +35 1100 +25 +40 +1 AVDD A V V mV mV mV mV mV mA V Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage Input Leakage Current (also DAT and JAM as inputs) X1 Crystal Input LOW Voltage X1 Crystal Input HIGH Voltage Crystal Input LOW Current Crystal Input HIGH Current IOL = 4.0 mA IOH = -0.4 mA DVSSAM79C981
1-95
AMD
PRELIMINARY
DC CHARACTERISTICS (continued)
Parameter Symbol Parameter Description Test Conditions Min Max Unit A K V V mV mV mV mV mV V V mV mV
Twisted Pair Ports IIRXD RRXD VTIVB VTID VTSQ+ VTSQVTHS+ VTHSVRXDTH VTXH VTXL VTXI VTXOFF RTXD RTXP Input current at RXD+/RXD differential input resistance RXD+,RXD- open circuit input voltage (bias) Differential Mode input voltage range (RXD) RXD positive squelch threshold (peak) RXD negative squelch threshold (peak) RXD post-squelch positive threshold (peak) RXD post-squelch negative threshold (peak) RXD switching threshold TXD+/- and TXP+/- output HIGH voltage TXD+/- and TXP+/- output LOW voltage TXD+/- and TXP+/- differential output voltage imbalance TXD+/- and TXP+/- differential idle output voltage TXD+/- differential driver output impedance TXP+/- differential driver output impedance DVDD = 5 V (Note 1) (Note 1) AVSSPower Supply Current IDD Power supply current (idle) Power supply current (transmitting - no TP load) Power supply current (transmitting - with TP load) fX1 = 20 MHz fX1 = 20 MHz fX1 = 20 MHz - - - 180 300 (Note 8) mA mA mA
1-96
AM79C981
PRELIMINARY
AMD
SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified
Parameter Symbol Parameter Description Test Conditions Min Max Unit
Clock and Reset tX1 tX1H tX1L tX1R tX1F tPRST tRST tRSTSET tRSTHLD X1 Clock Period X1 Clock HIGH X1 Clock LOW X1 Clock Rise Time X1 Clock Fall Time Reset pulse width after power on (RST pin LOW) Reset pulse width (RST pin LOW) RST HIGH setup time with respect to X1 Clock RST LOW hold time with respect to X1 Clock 49.995 20 20 - - 150 4 20 0 50.005 30 30 10 10 - - - - ns ns ns ns ns s s ns ns
Management Port tSCLK tSCLKH tSCLKL tSCLKR tSCLKF tSISET tSIHLD tSODLY tX1HCRS tX1HSTH tX1HSTL tTESTSET tTESTHLD tSTRSET tSTRHLD Expansion Port tX1HRL tX1HRH tX1HDR tX1HDZ X1 rising edge to REQ driven LOW X1 rising edge to REQ driven HIGH X1 rising edge to DAT/JAM driven X1 rising edge to DAT/JAM not driven CL = 100 pF CL = 100 pF CL = 100 pF CL = 100 pF 14 14 14 14 40 40 40 40 ns ns ns ns SCLK Clock Period SCLK Clock HIGH SCLK Clock LOW SCLK Clock Rise Time SCLK Clock Fall Time SI input setup time with respect to SCLK rising edge SI input hold time with respect to SCLK rising edge SO output delay with respect to SCLK rising edge X1 rising edge to CRS valid X1 rising edge to STR HIGH X1 rising edge to STR LOW TEST input setup time with respect to SCLK rising edge TEST input hold time with respect to SCLK rising edge STR setup time STR hold time CL = 100 pF CL = 100 pF CL = 100 pF CL = 100 pF 100 30 30 - - 10 10 - 5 - - 10 10 5 12 - - - 10 10 - - 40 40 40 40 - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
AM79C981
1-97
AMD
PRELIMINARY
SWITCHING CHARACTERISTICS (continued)
Parameter Symbol Parameter Description Test Conditions Min Max Unit
Expansion Port (Continued) tDJSET tDJHOLD tCASET tCAHOLD tMHSET tMHHLD tSCLKSET tSCLKHLD AUI Port tDOTD tDOTR tDOTF tDORM tDOETD tPWODI tPWKDI tPWOCI tPWKCI X1 rising edge to DO toggle DO+,DO- rise time (10% to 90%) DO+,DO- fall time (90% to 10%) DO+,DO- rise and fall time mismatch DO+/- End of Transmission DI pulse width accept/reject threshold DI pulse width maintain/turn-off threshold CI pulse width accept/reject threshold CI pulse width maintain/turn-off threshold |VIN| > |VASQ| (Note 3) |VIN| > |VASQ| (Note 4) |VIN| > |VASQ| (Note 5) |VIN| > |VASQ| (Note 6) - 2.5 2.5 - 275 15 136 10 90 30 5.0 5.0 1.0 375 45 200 26 160 ns ns ns ns ns ns ns ns ns DAT/JAM setup time DAT/JAM hold time COL/ACK setup time COL/ACK hold time TEST setup time with respect to RST to enter Minimum Hub Mode TEST hold time with respect to RST to enter Minimum Hub Mode SI, SCLK set up time with respect to X1 SI, SCLK hold time with respect to X1 10 14 5 14 200 0 50 50 - - - - - 100 - - ns ns ns ns ns ns ns ns
Twisted Pair Ports tTXTD tTR tTF tTM tTETD tPWKRD tPERLP tPWLP tPWPLP X1 rising edge to TXD+,TXP+ TXD-,TXP- transition delay TXD+,TXD-,TXP+,TXP- rise time TXD+,TXD-,TXP+,TXP- fall time TXD+,TXD-,TXP+,TXP- rise and fall time mismatch Transmit End of Transmission RXD pulse width maintain/turn-off threshold Idle signal period Idle Link Test pulse width (TXD+) Idle Link Test pulse width (TXP+,TXP-) |VIN| > |VTHS| (Note 7) - - - - 275 130 8 75 40 50 20 20 6 375 200 24 120 60 ns ns ns ns ns ns ms ns ns
1-98
AM79C981
PRELIMINARY
AMD
SWITCHING CHARACTERISTICS (continued)
Notes: 1. Parameter not tested. 2. Uses switching test load. 3. DI pulses narrower than tPWODI (min) will be rejected; pulses wider than tPWODI (max) will turn internal DI carrier sense on. 4. DI pulses narrower than tPWKDI (min) will maintain internal DI carrier sense on; pulses wider than tPWKDI (max) will turn internal DI carrier sense off. 5. CI pulses narrower than tPWOCI (min) will be rejected; pulses wider than tPWOCI (max) will turn internal CI carrier sense on. 6. CI pulses narrower than tPWKCI (min) will maintain internal CI carrier sense on; pulses wider than tPWKCI (max) will turn internal CI carrier sense off. 7. RXD pulses narrower than tPWKRD (min) will maintain internal RXD carrier sense on; pulse wider than tPWKRD (max) will turn internal RXD carrier sense off. 8. For the typical twisted pair load as shown in Figure 7, using a 100 cable, an additional 28 mA (max) of IDD current is required for each twisted pair port used. Less than 18% of the power associated with this additional current is dissipated by the IMR+ chip; the remainder is dissipated externally in the twisted pair load and cable.
AM79C981
1-99
AMD
PRELIMINARY
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Be Steady May Change from H to L May Change from L to H Don't Care Any Change Permitted Does Not Apply OUTPUTS Will Be Steady Will Be Changing from H to L Will Be Changing from L to H Changing State Unknown Center Line is High Impedance "Off" State
KS000010
SWITCHING WAVEFORMS
tX1 tX1H tX1L
X1
tX1R
tX1F
17306B-15
Clock Timing
1-100
AM79C981
PRELIMINARY
AMD
SWITCHING WAVEFORMS
X1 tRSTHLD RST
tRSTSET tRST or tPRST TCK*
Notes: tRSTSET refers to synchronous Reset Timing. *Externally generated (Figure 4) signal illustrates internal IMR+ device clock phase relationships.
17306B-16
Reset Timing
tSCLK
tSCLKF
tSCLKR
SCLK
tSCLKH
tSCLKL
SI/TEST
tSISET tTESTSET
tSIHLD tTESTHLD
SO
tSODLY
tSODLY
17306B-19
Management Port Clock Timing
AM79C981
1-101
AMD
PRELIMINARY
SWITCHING WAVEFORMS
X1
TCK*
REQ
ACK
COL tDJSET DAT JAM tDJHOLD
IN
Note: *Externally generated (Figure 4) signal illustrates internal IMR+ chip clock phase relationships.
17306B-20
Expansion Port Input Timing
X1
TCK*
tX1HRL REQ tCASET
tX1HRH
tCASET
ACK tCAHOLD COL tX1HDR DAT JAM tX1HDZ
OUT
Note: *Externally generated (Figure 4) signal illustrates internal IMR+ chip clock phase relationships.
17306B-21
Expansion Port Output Timing 1-102 AM79C981
PRELIMINARY
AMD
SWITCHING WAVEFORMS
X1
TCK* tX1HRL REQ tX1HRH
ACK tCASET COL tCAHOLD DAT JAM IN IN
17306B-22
tCASET
Note: *Externally generated (Figure 4) signal illustrates internal IMR+ chip clock phase relationships.
Expansion Port Collision Timing
Test tMHSET tMHHLD
RST
17306B-23
To Enter Minimum Mode
X1
STR tX1HSTH SI, SCLK tX1HSTL
Don't Care
Don't Care
tSCLKSET
tSCLKHLD
17306B-24
Minimum Mode AM79C981 1-103
AMD
PRELIMINARY
SWITCHING WAVEFORMS
1 X1 tDOTD tDOTR tDOTF tDOETD 0 1 1 1 0 1 0 ETD
D0+
D0-
17306B-25
AUI DO Timing Diagram
tDOETD
DO+/-
40 mV 100 mV max.
0V
80-Bit Times
17306B-26
AUI Port DO ETD Waveform
tPWKDI
DI+/- VASQ tPWKDI tPWODI
17306B-27
AUI Receive Timing Diagram
1-104
AM79C981
PRELIMINARY
AMD
SWITCHING WAVEFORMS
tPWKCI CI+/- VASQ tPWOCI
tPWKCI
17306B-28
AUI Collision Timing Diagram
1 X1
0
1
0
1
1
1
0
1
0
ETD
tTXTD TXD+ tTXTD TXP+
tTXTR
tXTXTF
tTXETD
TXD-
TXP-
17306B-29
TP Ports Output Timing Diagram
AM79C981
1-105
AMD
PRELIMINARY
SWITCHING WAVEFORMS
tPWPLP
TXD+
TXP+ tPWPLP TXD-
TXP-
tPWLP
tPERLP
17306B-30
TP Idle Link Test Pulse
VTSQ+ RXD+/- VTSQ-
17306B-31
tPWKRD
VTHS+ VTHS-
tPWKRD
tPWKRD
TP Receive Timing Diagram
1-106
AM79C981
PRELIMINARY
AMD
SWITCHING TEST CIRCUITS
AVDD
52.3 DO+ DO- 100 pF Includes Test Jig Capacitance 154 Test Point
AVSS
17306B-32
AUI DO Switching Test Circuit
DVDD
294 TXD+ TXD- 100 pF Includes Test Jig Capacitance 294 Test Point
DVSS
17306B-33
TXD Switching Test Circuit
DVDD
715 TXP+ TXP- 100 pF Includes Test Jig Capacitance 715 Test Point
DVSS
17306B-34
TXP Outputs Test Circuit AM79C981 1-107
APPENDIX
A
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10BASE-T INTERFACE
The table below lists the recommended resistor values and filter and transformer modules for the IMR+ device.
IMR+ Device Compatible 10BASE-T Media Interface Modules
Manufacturer Part #
S556-5999-32 0556-2006-14 A556-2006-DE A556-2006-00 FS02-101Y4 FS12-101Y4 FS22-101Y4 FD02-101G FD12-101G FD22-101G FD22-101R2 5408-37 5408-40 6612-21 EPA1990A EPA1990AG EPA2013D EPA2013DG 78Z034C 78Z1120B-01 78Z1122B-01 PE-68017S PE-68026 PE-68056 PE-68032 TLA-3M601-RS TLA-3M102(-T) TLA-3M103(-T) PT3877 PT3983 FL1012
Package
16-pin SMD 10-pin SIL 16-pin 0.3" DIL 16-pin DIL "Slim SIP" "Slim SIP" "Slim SIP" 16-pin 0.3" DIL 16-pin 0.3" DIL 16-pin 0.3" DIL 16-pin 0.3" DIL 16-pin SMD 9-pin SIP 12-pin DIL 16-pin 0.3" DIL SMT device 16-pin 0.3" DIL SMT device 16-pin DIL 16-pin DIL 16-pin DIL 10-pin SIL 16-pin SMT 16-pin SMT 13-pin PCMCIA-SMT 10-pin SIP 16-pin SMD 16-pin SMD 16-pin 0.3" DIL 8-pin 0.3" DIL 16-pin 0.3" DIL
Description
Transmit and receive filters, transformers and common mode chokes. Transmit and receive filters, transformers and common mode chokes. Transmit and receive filters and transformers. Transmit filter, transformers and common mode choke. Receive filter and transformer. Transmit and receive filters and transformers. Transmit and receive filters and transformers, transmit common mode reduction choke. Transmit and receive filters, transformers and common mode chokes. Transmit and receive filters and transformers. Transmit and receive filters and transformers, transmit common mode choke. Transmit and receive filters, transformers and common mode chokes. Termination and equalization resistors, transmit and receive filters, transformers and common mode chokes. 7 pole transmit and receive filters with 1CT:1CT Xfmrs (transmit & receive) and a separate common mode choke for each channel. 7 pole transmit and receive filters with 1CT:1CT Xfmrs (transmit & receive) and a separate common mode choke for each channel. 7 pole transmit and receive filters with 1CT:1CT Xfmrs (transmit & receive) and a separate common mode choke for each channel. Transmit and receive filters and transformers. Transmit and receive filters and transformers. Transmit and receive filters and transformers, transmit common mode choke. Transmit and receive filters and transformers, transmit common mode choke. Transmit and receive filters and transformers, transmit common mode chokes. Transmit and receive filters and transformers. Transmit and receive filters, transformers and common mode chokes. Transmit and receive filters, transformers and common mode chokes. Transmit and receive filters, transformers and common mode chokes. Transmit and receive filters, transformers and common mode chokes. Transmit and receive filters and transformers, transmit common mode chokes. Transmit and receive filters and transformers, transmit common mode chokes. Integrated resistors, transmit and receive filters and transformers, transmit common mode chokes. Transmit and receive filters and transformers, transmit common mode chokes. Transmit and receive filters and transformers. Transmit and receive common mode chokes. Transmit and receive filters and transformers, transmit common mode chokes.
1-108
AM79C981
APPENDIX B
Glossary
Active Status In a non-collision state, an IMR+ chip is considered active if it is receiving data on any one of its network ports, or is in the process of broadcasting (repeating) FIFO data from a recently completed data reception. In a collision state (the IMR+ device is generating Jam Sequence), an IMR+ device is considered active if any one or more network ports is receiving data. The IMR+ device asserts the REQ line to indicate that it is active. Collision In a carrier sense multiple access/collision detection (CSMA/CD) network such as Ethernet, only one node can successfully transfer data at any one time. When two or more separate nodes (DTEs or repeaters) are simultaneously transmitting data onto the network, a Collision state exists. In a repeater using one or more IMR+ devices, a Collision state exists when more than one network port is receiving data at any instant, or when any one or more network ports receives data while the IMR+ device is transmitting (repeating) data, or when the CI+/- pins become active (nominal 10 MHz signal) on the AUI port. Jam Sequence A signal consisting of alternating 1s and 0s that is generated by the IMR+ device when a Collision state is detected. This signal is transmitted by the IMR+ device to indicate to the network that one or more network ports in the repeater is involved in a collision. Network Port Any of the eight 10BASE-T ports or the AUI port present in the IMR+ device (i.e. not the Expansion Port or the Management Port). Partitioning A network port on a repeater has been partitioned if the repeater has internally `disconnected' it from the repeater due to localized faults that would otherwise bring the entire network down. These faults are generally cable shorts and opens that tend to cause excessive collisions at the network ports. The partitioned network port will be internally re-connected if the network port starts behaving correctly again, usually when successful `collisionless' transmissions and/or receptions resume. Receive Collision A network port is in a Receive Collision state when it detects collision and is not one of the colliding network `nodes'. This applies mainly to a non-transmitting AUI port because a remote collision is clearly identified by the presence of a nominal 10 MHz signal on the CI+/pins. However, any repeater port would be considered to be in a receive collision state if the repeater unit is receiving data from that port as the `one-port-left' in the collision sequence. Transmit Collision A network port is in a Transmit Collision state when collision occurs while that port is transmitting. On the AUI port, Transmit Collision is indicated by the presence of a nominal 10 MHz signal on the CI+/- pins while the AUI port is transmitting on the DO+/- pins. On a 10BASE-T port, Transmit Collision occurs when incoming data appears on the RXD+/- pins while the 10BASE-T port is transmitting on the TXD+/- and TXP+/- pins.
AM79C981
1-109
1-110
AM79C981

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